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| TEST AND MEASUREMENT PRODUCTS Description The E7804 is a quad channel, monolithic ATE pin electronics solution manufactured in a high-performance BiCMOS process. The E7804 operates up to 33 MHz with up to 3V signals, and 00 MHz with 5V signals. Each channel has a three-statable driver capable of generating 5.4V swings over a -0.2V, +5.2V range. Drivers have independent high and low input levels that are buffered internally. Drivers feature a self-calibrating source impedance, programmable in the range 48 to 110. The source impedance of all drivers matches REREF/00, where REREF is the external reference resistor. Each channel's dual comparator has a range of -2.0V to +5.5V. A channel's driver and comparators are connected internally via high voltage switches to the VIO pin. These switches provide a means to disconnect the driver and comparator from the VIO pin. The E7804 contains an independent network of high voltage switches intended to connect an external Parametric Measurement Unit (EPMU) to any channel (or channels) output on the channel's POUT pin. The EPMU can have a range of -4.75V to +9.75V, up to 40 mA. Typically, a channel's VIO and POUT pins are connected together externally. Each channel contains a continuity test circuit (CTC) with a switch to connect it to the channel's POUT pin. This circuit forces a current up to -250 A, and tests the resulting voltage with a 0 to -2V programmable limit. The result is tested by the channel's comparator. Each channel contains a 2K pull-up resistor with a switch to connect to the channel's POUT pin. The channel's function and connections are programmed using a serial interface. An individual channel's function can be programmed, or a function of any set of channels (of multiple E7804s) can be programmed in parallel where each channel can belong to none, one, or more (up to 8) sets. The E7804 features the inclusion of all four channels of pin electronics into a 28 pin package. Revision 7 / February 26, 2007 133 MHZ Quad Pin Electronics Driver and Window Comparator Features * Four Integrated Three-Statable Drivers and Window Comparators * Driver Voltage Range -0.2V, +5.2V * Comparator Voltage Range -2.0V to +5.5V * Internal Disconnect Switches * Internal Switches to an External PMU, Range -4.75V to +9.75V, up to 40 mA * Per Pin Pull-Up/Down 2K to (0V to +5V) * Per Pin Continuity Test (Force Current up to -250 A, Limit Voltage 0 to -2V) * Self-Calibrating Driver Source Impedance to an External Reference (48 to 110) * Low Power Dissipation (250mW/channel quiescent) * 28 Pin MQFP Package (with Internal Heat Spreader) E7804 Applications * Design for Test/Structural Pins in ATE * Low Cost - Logic Testers - Memory Testers Functional Block Diagram PUV EPMUS EPMUF CTCLV CTCFIV SDIN CLKIN EREF DVH[0] DHI[0] DEN[0] DVL[0] OPN[0] CVA[0] QA[0] QB[0] CVB[0] 48 110 VIO[0] POUT[0] CTC 2K Control Logic LOAD RESET* DVH[3] DHI[3] DEN[3] DVL[3] OPN[3] CVA[3] QA[3] QB[3] CVB[3] 48 110 VIO[3] POUT[3] CTC 2K SDOUT ANODE PMU_OUT United States Patent 7,064,575 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS PIN Description Pin # Driver, Comparator 12, 27, 76, 91 OPN[0:3] LV_TTL input that opens switches that disconnect the driver and comparator from VIO. This input overrides the individual switch register bits non destructively. Device input/output of each channel. Pin Name Description 15, 24, 79, 88 127, 40, 63, 104 128, 39, 64, 103 1, 38, 65, 102 2, 37, 66, 101 126, 41, 62, 105 125, 42, 61, 106 16, 23, 80, 87 14, 25, 78, 89 124, 43, 60, 107 123, 44, 59, 108 10, 29, 74, 93 9, 30, 73, 94 8, 31, 72, 95 7, 32, 71, 96 PMU 111 5, 34, 69, 98 110 109 114 120 118 Control 54 51 50 49 53 VIO[0:3] DHI, DHI*[0:3] "Flex" differential input digital pins which select the driver high or low level. DEN, DEN*[0:3] "Flex" differential input pins which control the driver being active or in a high impedance state. DVH, DVL[0:3] High impedance analog voltage inputs which determine the driver high and low levels. Connect a 0.22f capacitor to ground for bypassing reasons. DBH, DBL[0:3] Driver level buffer outputs for high and low levels. Connect a 0.47 F capacitor to ground for bypassing reasons. CVA, CVB[0:3] Analog inputs which set the A and B comparator thresholds. QA, QA*[0:3] QB, QB*[0:3] Differential digital outputs of comparator A. Differential digital outputs of comparator B. PMU_OUT POUT[0:3] EPMUF EPMUS PUV CTCLV CTCFIV RESET* CLKIN SDIN SDOUT LOAD PMU test point for the anode of the thermal diode string. Parametric Measure Unit input/output of each channel. External parametric measurement for force input. External parametric measurement for sense input. Pull-up voltage input. Continuity test circuit limit voltage. Continuity test circuit force current voltage. Active low chip reset. Resets the internal registers. It is an asynchronous input not requiring any CLKIN transitions. Clock for the input data shift register. Serial data input. Serial data out. Loads input data into central register. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 2 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS PIN Description (continued) Pin # Power Supplies 11, 28, 75, 92 117 6, 33, 70, 97 113 13, 26, 77, 90, 115 17, 22, 81, 86 46, 47, 48 19, 20, 83, 84 55, 56, 57, 119 121 Miscellaneous 116 112 EREF ANODE External reference resistor input. REREF should be connected between EREF and AGND. Anode terminal of the on-chip thermal diode string. The pin is ESD protected to VXX, so when measuring the forward drop of the diode string, VXX should be either floating or 2V. Cathode of diode string is connected to DGND. No connect pin. No connection is made internally. These pins can be connected to a ground plane to assist in heat removal from the package. Pin Name VCC[0:3] VCC VAA[0:3] VAA VEE VDD[0:3] VDD AGND[0:3] DGND VXX Description Analog positive power supply to channel high voltage circuitry (+8.25V). Analog positive power supply to high voltage circuitry (+8.25V). Analog positive power supply to channel circuitry (+5.0V nominal). Analog positive power supply to core circuitry (+5.0V nominal). Analog negative power supply (-5.0V nominal). Digital positive power supply to channel comparator outputs (+3.3V nominal). Digital positive power supply for core logic (+3.3V nominal). Analog ground for channels. Digital ground for chip. Switch positive power supply (VCC to VEE + 15V). 3, 4, 18, 21, 35, 36, 45, 52, 58, 67, 68, 82, 85, 99, 100, 122 NC (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 3 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Pin Description (continued) PMU_OUT CTCFIV EPMUS ANODE EPMUF DVH[0] DVH[3] 105 DHI*[0] 119 118 117 116 115 114 113 112 111 128 127 126 125 124 123 122 121 120 110 109 108 107 106 104 DEN[0] DEN*[0] NC NC POUT[0] VAA[0] QB*[0] QB[0] QA*[0] QA[0] VCC[0] OPN[0] VEE DBL[0] VIO[0] DBH[0] VDD[0] NC AGND[0] AGND[1] NC VDD[1] DBH[1] VIO[1] DBL[1] VEE OPN[1] VCC[1] QA[1] QA*[1] QB[1] QB*[1] VAA[1] POUT[1] NC NC DEN*[1] DEN[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 103 DHI*[3] CTCLV CVB[0] CVB[3] CVA[0] CVA[3] DVL[0] DVL[3] DGND DHI[0] DHI[3] EREF VCC PUV VXX VEE VAA NC 102 101 100 99 98 97 96 95 94 93 92 DEN[3] DEN*[3] NC NC POUT[3] VAA[3] QB*[3] QB[3] QA*[3] QA[3] VCC[3] OPN[3] VEE DBL[3] VIO[3] DBH[3] VDD[3] NC AGND[3] AGND[2] NC VDD[2] DBH[2] VIO[2] DBL[2] VEE OPN[2] VCC[2] QA[2] QA*[2] QB[2] QB*[2] VAA[2] POUT[2] NC NC DEN*[2] DEN[2] E7804 128 Pin MQFP 14 x 20 mm 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 DHI*[2] CVA[1] CVB[1] CVB[2] CVA[2] DHI[1] SDOUT DVL[1] DHI*[1] DVH[1] DVL[2] RESET* (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 4 DVH[2] CLKIN DGND DGND DGND DHI[2] LOAD SDIN NC VDD VDD VDD NC NC www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description CTCFIV EPMUS EPMUF CTCLV CLKIN DGND DBH[0] DVH[0] DHI[0] DHI*[0] DEN[0] DEN*[0] 48 110 S3[0] REREF VCC[0] VAA[0] VDD[0] VIO[0] POUT[0] AGND[0] VEE[0] 2K VCC[3] VAA[3] VDD[3] VIO[3] POUT[3] AGND[3] VEE[3] 2K CONTLV SDIN DVL[0] DBL[0] S1[0] OPN[0] CVA[0] QA*[0] QA[0] QB[0] QB*[0] CVB[0] S2[0] A B VINP ~50K S4[0] S5[0] CTC S6[0] Control Logic LOAD RESET* DBH[3] DVH[3] DHI[3] DHI*[3] DEN[3] DEN*[3] 48 110 S3[3] S1[3] DVL[3] DBL[3] OPN[3] CVA[3] QA*[3] QA[3] QB[3] QB*[3] CVB[3] S2[3] A B VINP ~50K S4[3] S5[3] CTC S6[3] S7 SDOUT Figure 1. Detailed Block Diagram of E7804 Quad Driver and Window Comparator DGND ANODE PMU_OUT EREF VDD PUV VXX CONTINUITY TEST CIRCUIT (CTC) (Force I, Limit V) ICTC CONTFIV (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 5 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Introduction The four driver and window comparator channels of the E7804 are shown in Figure . Driver Refer to Table showing the modes of operation of the driver. Each channel's driver states of HiZ, force DVH voltage, force DVL voltage and Open can be controlled either by external input pins or via internal registers and bits programmed through the serial interface. The HiZ/DVH/DVL states are controlled by the differential, external inputs, DHI/DHI* and DEN/DEN*. Each channel also has internal register bits (see Table 2, CH[0:3]_Relays_ &_States registers) SDHI and SDEN that accomplish the same functions as DHI and DEN. The serial register has another bit, SEN (Serial Enable) that allows the SDI and SDEN bits to override the external input pins DHI and DEN. If SEN is a logical "0", the SDHI and SDEN bits are ignored. The DHI/DHI* and DEN/DEN* inputs are LV_TTL and differential LVDS, LV_PECL compatible. Unused DHI/DHI* or DEN/DEN* must be tied to valid logic levels. Optimizing Driver Waveforms The driver output pin, VIO, will normally be connected to the parametric output pin, POUT, when designed into a system. See the recommended 7804 Hookup drawing farther on in this datasheet. The POUT pin has a lumped capacitance associated with it that will degrade the signal integrity of the driver output waveform if not properly compensated for. The recommendation is to insert ferrite devices between the connection of POUT to VIO to accomplish this. For more details on how and why this approach is used, please read Semtech Application Note #ATE-A3 ATE-to-DUT Interface: Using Ferrites to Replace Relays for Lower Cost and Improved Performance. The driver output impedance has a reactive component to it and will not completely absorb reflections from an (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 6 unterminated transmission line. This is common for all drivers, but more so in CMOS drivers than high speed bipolar stages. The figure here shows how transmission line length, here in the form of coaxial cable, will sum the reflections constructively and destructively to alter the peak-to-peak waveform excursions across frequency. More data on this performance and methods for optimizing signal integrity and extending Fmax will be available from Semtech staff. Check with Semtech for the latest information. From the graph below one can see that E7804 driver signals in excess of 50MHz are possible. Driver Levels Each channel's DVH and DVL are high input impedance voltage inputs which establish the channel driver's high and low levels. The driver's output range is -0.2V, +5.2V. DVH to VIO and DVL to VIO offset errors are small, which allow the E7804 to be configured with common input levels to each channel (i.e. DVH[0:3] may be connected together externally, and the same for DVL[0:3]). Driver Source Impedance Drivers feature a self-calibrating source impedance calibrated to match an external resistor, REREF, connected between the EREF pin and analog ground. The source impedance can be chosen to calibrate in the range 48W to 0W using the calculation REREF/00. A driver's source impedance is affected by its DVH and DVL levels, and therefore needs recalibrating whenever driver levels into the chip are changed. The calibration routine is initiated via the serial interface (see Table 2, calibrate_output_z register). When initiated, all channels are recalibrated in parallel. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Driver Connect/Disconnect The driver output connects to the VIO output pin through an internal, normally open switch (S). Refer to the Functional Block diagram in Figure for Switch S. This switch can be closed by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_Relays_ &_States registers) denoted as S to a logical "". Logical "0" will open the switch. An external pin, OPN[0:3] one input for each channel, is combined with the register bit and will override the internal register bit and Open the S switch for the channel. In its low state, the OPN input will not override and force the switch closed however. (It should be noted that OPN= will also open S2 to disconnect the channel's window comparators from the VIO pin.) OPN is a fast way of disconnecting the lower voltage driver and comparator circuitry from the VIO pin. When the driver (and comparator) are disconnected, the voltage at VIO may be in the range of the VEE to VXX power supplies. The high voltage disconnect switches permit an external Parametric Measurement Unit (PMU) to be connected to the VIO pin having a maximum range from VEE to VXX volts and up to 40 mA. This high voltage isolation also permits an external driver to apply up to VXX volts (when switches S and S2 are open) for high voltage applications. Each driver may also be connected, internally, to EPMUS in order to measure its output for purposes of calibrating the DVH/L levels via switch S3. OPN=0 Digital Inputs DEN 1 1 0 0 OPN DVL DVH HiZ DHI 0 1 0 1 (Open Channel Input) (Driver Low) (Driver High) (High Impedance) S1 Closed VIO DVL DVH HiZ HiZ Open X S1 S1 Open VIO Open Open Open Open OPN=1 X VIO Open Open Open Open Comparator Each channel's two comparators, A and B, are combined to form a window comparator to determine whether its input, VINP, is above, below, or in between the two comparator thresholds (CVA and CVB). VINP is tied to the positive input of both comparators. The CVA/B inputs should be driven from low impedance sources. There is an input non-linear current shift of ~5A when the VINP signal to the comparator crosses polarity with respect to the CVA/B input. If the source impedance is too great, this could affect the accuracy of the compare points. The voltage source's output impedance should be below 4KW to avoid this. DAC or op amp outputs will have no issue with this. (If resistor dividers are used to create the CVA/B voltages, the voltage should be buffered to prevent this shift.) VINP has a range of -2V, +5.5V, but is restricted to the range of the drivers whenever a comparator is connected to its driver (S and S2 switches both closed), namely -0.2V, +5.2V. The comparator outputs are differential LVDS compatible on the QA/QA* and QB/QB* device pins. The output states of the comparators for each channel can also be read back using the serial interface. See Table 3, CH[0:3]_switches_&_states read back instruction for the individual channels. Comparator Levels Each channel's CVA and CVB are the window comparator's two threshold levels. CVA and CVB are high impedance voltage inputs that determine the thresholds at which the window comparator changes state. CVA and CVB have a range of -2.0V, +5.5V. Comparator Connect/Disconnect The window comparator input (VINP) connects to the VIO pin through an internal switch (S2). This switch can be closed to VIO by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_switches_&_states registers) denoted as S2 to a logical "". Logical "0" will open the switch from VIO. The comparator input is connected to approximately zero volts 7 www.semtech.com (Driver, Comp open/disconnected (see Table 3) (Don't Care) (Driver Output Switch Table 1. Driver Modes of Operation (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) when disconnected from VIO through ~50KW. To prevent the comparator outputs from switching due to noise when not in use, the CVA/B inputs should be parked >250mV from ground. An external pin, OPN[0:3] one input for each channel, is combined with the register bit, and will override the internal register bit and open the S2 switch for the channel. In its low state, the OPN input will not override and force the switch closed. (It should be noted that OPN= will also open S to disconnect the channel's driver output from the VIO pin.) OPN is a fast way of disconnecting the lower voltage driver and comparator circuitry from the VIO pin. When the comparator (and driver) are disconnected, the voltage at the VIO pin may be in the range of the VEE to VXX power supplies. Parametric Measurements The E7804 incorporates a switch matrix which permits an External Parametric Measurement Unit (EPMU) to be connected to one or more channel's POUT pin. The EPMU range is a function of the VEE and VXX power supplies with 40 mA capability. Typically, POUT is connected directly to the VIO pin or connected by an inductor so as to minimize the effect of the capacitance at the POUT pin on the driver's waveform and maximum frequency. The EPMUF and EPMUS inputs are force and sense inputs respectively and connect to the POUT output pin through an internal, normally open, dual switch (S4). There is one dual switch for each channel [0:3]. This switch can be closed by serially programming the internal register bit for the appropriate channel (see Table 2, CH[0:3]_switches_&_states registers) denoted as S4 to a logical "". Logical "0" will open the switch. The switch and metal lines for the EMPUF path are sized to accommodate the higher currents (up to 40mA). Do not use EPMUS for higher currents. The EPMUS line is the Kelvin sense path for the external PMU. Continuity Test Circuit Each channel has a programmable Continuity Test Circuit (CTC) which can be switched to its POUT pin. The CTC sinks current in the range -5 to -250 A as determined by the voltage of the CTCFIV input pin which is common to all CTC's. The relationship between the CTCFIV input voltage and the resulting current produced by the CTC uses the resistor REREF, as a reference. This gives a good degree of voltage to current accuracy. The relationship is: ICTC = -.09 * [CTCFIV(V) / REREF(W)]. CTCLV input determines the voltage limit to which CTC may sink current. CTCLV has a range of 0 to -2.0V and is common to all channels' CTCs. With POUT, connected externally to VIO, then with CTC connected and sinking current, the resultant voltage at VIO can be tested by the channel's comparators. As this voltage could be as low as -2V, when performing a continuity test, a channel's driver should be disconnected in order to protect the driver, which has a range of -0.2V to +5.2V. The driver output should be disconnected by opening switch S when connecting the CTC to the POUT pin. The CTC connects to the POUT pin through the normally open switch S5. Switch S5 can be closed by serially programming a logical "" via the internal register for the appropriate channel. See Table 2,"CH[0:3]_switches_&_states write instruction for the individual channels. Note that the CTC's use the external resistor on the EREF pin to calculate the ICTC test currents. The driver output impedance calibration also uses this reference. If any CTC is switched in-circuit (S5 closed), then attempting to calibrate the driver output impedance will fail and not occur. No change to the calibration values will take place. A typical continuity test will program the CTC's force current to -00 A, its voltage limit at -2V, and CVA and CVB at -0.5V and -.5V, respectively, so as to detect shorts, opens and continuity. typically, in this test, the DUT power supplies are all set to zero volts. The continuity test will determine if each pin of the DUT is connected to the pin channel in the tester without shorts to supplies or ground. 0V CVA = -0.5V CVB = -1.5V CTCLV = -2V Short Continuity Open The tested pins will test good if the resulting voltage from a -00A load on them results in ~-0.7V. This is the voltage (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 8 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) that will be present if the pin substrate or ESD diodes are present. A short can be detected if the resulting voltage is close to zero volts. An Open will be detected if the voltage goes close to -2V. The figure above ilustrates this test with the CVA =- 0.5V and CVB = -.5V. Pull-Up Resistor Each channel has a 2KW (typ.) pull-up resistor that can be switched to its POUT. The effective pull-up, including resistor and switch, is in the range KW to 3KW. PUV is a single input and is buffered at each channel to the pull-up resistors. The buffer and resistor are capable of sourcing or sinking (pull-up or pull-down) currents for 0 to 5V external signals. Thermal Monitor An on-chip thermal diode string of three diodes in series allows accurate die temperature measurements (see diagram below). A bias current of 00 A is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: Tj[ C] = (0.795 - VANODE/3) / (0.00967) F S PMU_OUT ANODE D12 MSB Programming Functional Description The E7804 features a serial data input programming structure to program the channels functions and switches, assign or invoke Set functions, as well as control more global chip functions such as Reset and Calibration. The majority of the functions are both Read and Write. The serial streams are all 24-bits long and are referred to as "instructions" because the serial streams are built up with address, function, read and select bits as well as data into the 24-bit stream which is clocked serially into the device. The following is a description of the 24-bit instruction stream. Chan/Set Data Bits D11 D1 D0 LSB Chan/Set Bit Last Bit Written Bit #24 Mode Bit First Bit Written Bit #1 A3 Address A2 A1 A0 F3 Read/Write Bit Function F2 F1 F0 Data: 13 bits This field contains the data to be written into various registers which control the function of the part, or the selected channel(s). Channel/Set Address Select: 1 bit Bias Current This bit determines whether a single channel or a set of channels is being addressed. 0 = channel direct functions = set of channels Channel/Set Address: 4 bits Temperature Coefficient = -5.9mV/oC The ANODE of the diodes may be switched internally to the EPMU bus such that temperature measurements can be performed by the EPMU. The connection to the diode string's ANODE pin for the EPMU is performed externally by shorting the PMU_OUT pin to the ANODE pin. This external connection is available to make it possible to access the diode string when the device is not powered up. This is useful for calibration purposes of the diode string. The ANODE pin is internally ESD protected in the positive direction to VXX. To use the diode string, VXX needs to either be floating (unpowered operation) or 2V. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 This field contains the address of the channel or set being operated on. Mode: 1 bit This determines whether the instruction refers to a chiplevel control (such as chip reset), or refers to a channel or set of channels. 0 = chip function = channel or set function 9 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Read/Write: 1 bit This determines whether a particular address/function is being written or read. (Note that some functions are readonly or write-only). 0 = write a control/data register = read back the contents of a register Function: 4 bits supplies become stable in order to put the E7804 into a known starting state. After power-up, the RESET* may be exercised or a soft reset instruction may be programmed. Write Serial Data Data is shifted into the WRITE shift register using CLKIN. The data stored in the shift register will be stored into the E7804 by asserting the LOAD input signal during the 24th CLKIN high-going edge. The LATCH will hold the instruction inside the E7804 for address decoding and data storage into the appropriate on-chip registers. Seven (7) more CLKIN high-going edges should be given after a LOAD for full decode and all instruction executions. Refer to Figure 3 for a timing diagram of the writing operation. Notice that the SDOUT data that is clocked out on the low-going edge of CLKIN is a bit for bit representation of the data that had been shifted into the E7804 24 clock edges beforehand. This echoing of the data allows the user to "daisy chain" multiple E7804 devices to minimize the number of serial data streams that need to be implemented. The compromise is the length of time it takes to clock through all the 24-bit instructions for all the devices in the chain. "Don't Care" D[0:4] This determines which function within a channel or set is being set or read. Refer to Figure 2 for a block diagram of the Write and Read logic for the serial programming. The serial data is input into the device SDIN pin. The data at SDIN is clocked in on the high-going edge of the CLKIN input signal. The data at the SDOUT pin is clocked out on the low-going edge of the CLKIN input signal for ease of "daisy chaining" multiple devices. RESET* There is a single input pin to the entire E7804 chip that will clear all on-chip registers and open all on-chip switches. This input pin, RESET*, is active low and is asynchronous, not requiring any CLKIN transitions to operate. It is advised that, upon power-up in a system, this pin is either held low or cycled low for a brief time while the system and power DATA D[20:24] SIN D[5:17] READBACK 24-Bit Shift Register RESET SOUT - READ RESET* 13 10 ADR Read Bit Only True for 24 Clocks DATA CK RESET 24 READBIT SDOUT CLKIN LOAD LATCH SDIN Q WRITE 24-Bit Shift Register RESET SOUT - WRITE Figure 2. Block Diagram of Read and Write Shift Registers (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 0 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) First Instruction "N" Instruction "N+1" Instruction "N+2" SDIN Bit 22N Bit 23N Bit 0N+1 Bit 1N+1 Bit 22N+1 Bit 23N+1 Bit 0N+2 Bit 1N+2 Bit 22N+2 Bit 23N+2 CLKIN LOAD SDOUT Bit 0N Bit 22N Bit 23N Bit 0N+1 Bit 1N+1 Bit 21N+1 Bit 22N+1 Bit 23N+1 Bit 0N+2 Instruction "N" Echo Instruction "N+1" Echo Figure 3. Serial Data Programming - Write Instruction Figure 4 depicts two topologies to serially read and write multiple E7804 devices on a single assembly. Figure 4a daisy chains the serial I/O (SDOUT to SDIN) pins, and the CLKIN and LOAD functions are common for all the E7804s. This topology uses a minimum amount of I/O from the control logic. However, in order to read or write the E7804's an instruction string of 24 x N bits long needs to be created, clocked all the way through the devices, and a parallel LOAD signal asserted for all devices. NO_OP instructions may be used for the devices that are not being addressed. Figure 4b shows a topology from the control logic that offers rapid programming time and complete independence. This topology relies on enough I/O signals being available from the control logic. Notice that the CLKIN pins are still all common because independence is allowed by the individual LOAD signals to each E7804. If it is determined that readback from the E7804s are not necessary, the control logic can be further simplified. Readback is not necessary for the operation of the E7804. It is offered as a good diagnostic tool and possible programming aid. Read Serial Data In order to readback data, an instruction is constructed with the Read_Bit set to a logical "" in the instruction (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 stream and written to the E7804. The instruction stream must be properly constructed for address and select bits to insure that the proper register will be accessed for readback. The data bits D0:D2 in this Read instruction are Don't_Care. Refer to Figure 5 for a timing diagram of the readback process and Figure 2 for a block diagram of how the readback operation works. Once the LOAD signal is asserted on the 24th high-going CLKIN edge to latch in the READ instruction for a particular address, the internal READ line will assert true and switch the SDOUT pin to output data from the internal readback shift register. The readback data will immediately start to output from the SDOUT pin on the low-going edge of CLKIN. The readback will continue for 24 bits. The first 5 bits of data readback should be ignored. The next 3 bits will be the requested register's readback data. Finally, the last 6 bits are logical zeros. While clocking out the readback data, a new instruction can be simultaneously clocked in at SDIN. At the conclusion of the 24-bit readback, the SDOUT data will revert back to echoing the SDIN data shifted by 24 clocks. www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) SDIN CLKIN LOAD CLKOUT SDIN CLKIN LOAD E7804 #1 SDOUT SOUT1 LOAD1 SIN1 E7804 #1 SDOUT SOUT CLKOUT LOADOUT SDIN CLKIN LOAD SOUT2 LOAD2 SIN2 SDIN CLKIN LOAD SIN E7804 #2 SDOUT E7804 #2 SDOUT DIGITAL ASIC SOUT"N" SDIN CLKIN LOAD LOAD"N" SIN"N" SDIN CLKIN LOAD E7804 "N" SDOUT DIGITAL ASIC E7804 "N" SDOUT a. Minimum # of Control Lines from ASIC b. Independent Control of Each E7804 Figure 4. Serial Control of Multiple E7804s Figure 5 depicts the conclusion of a Read instruction being written to the E7804. The first LOAD pulse straddling the rising edge of CLKIN latches in the Read instruction, echoing at SDOUT stops, and the readback of the register begins. After 24 low-going clocks, the data at SDOUT resumes echoing the written data at SDIN. Even without the second LOAD pulse, the echoing will begin. Figure 5 depicts a Write instruction following the Read. This could be another Read instruction, in which case the echoing of SDIN would not begin as indicated. Instead, another sequence of 24 readback bits would begin. The readback data format and address are defined in Table 3. The Read operation will continue for 24 low-going clock edges. The SDOUT will begin outputting data from the write shift register after the 24th low-going clock edge. Address Map Table 2 shows the Write Table and Address Map. Across the top of the table are the 24 bits of data denoted as Bit #0 through Bit #23. Hex notation is also provided as well as the binary positions. The instruction is constructed of 3 Data bits, 8 address bits, 2 select bits and a read bit. Figure 3 shows the bit pattern in the write instructions. The instructions are separated into 3 main groups. The Chip Functions, the Channel Functions and the Set Functions. Each instruction has a Register Name associated with it. In the pages following Table 2 are descriptions of each of the register names and, where applicable, a bit-by-bit description of the data. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 2 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Chip Functions The Chip Functions group of instructions controls chip functions that are global in scope and not associated with a particular channel. Examples of these functions are the chip identification number and revision, the Reset function for chip wide reset, and initiation of calibration. FunctionAddress - Instructions in the group are denoted by this set of bits. ReadBit-- Set to "" only if user intends to read back a register. ChanBit- Set to a "0" since this instruction group is not channel related. Chan/SetAdr - These 4 bits are "don't care". Since these would select either a channel or set number, and these are Chip Functions, they don't apply. SetSelectBit - This bit is a "don't care" for the Chip Functions group. Channel Functions The Channel Functions group of instructions address the functionality of individual registers and bits that are particular to specific channels of the E7804. Driver states, channel switches, calibration factors and set assignments are included in this group. FunctionAddress - These bits denote which function of the particular channels is being addressed. ReadBit-- Set to "" only if user intends to read back a register. ChanBit - Set to a "" because these instructions relate to specific channel registers. Chan/SetAdr - These bits will denote which channel is being addressed for the particular function. Valid range is 0x0 through 0x3 for the E7804. SetSelectBit - This bit is set to a "0" because this is the Channel Functions group. Read Instruction Next Instruction A Write Instruction Echo Begins 24 Clocks Later SDIN Bit 22 Bit 23 Bit 0 Bit 1 Bit 22 Bit 23 Bit 0 Bit 1 CLKIN LOAD SDOUT READ Bit 0 READ Bit 4 READ Bit 5 READ Bit 17 READ Bit 18 READ Bit 23 Bit 0 ECHO First 5 Bits Ignore 13 Bits Valid Readback Data 6 Bits Zero Fill 24 Bits Readback Figure 5. Serial Data Programming - Readback Sequence (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 3 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Set Functions Set Functions are a group of 8 instructions corresponding to the 8 available Sets that will configure any channel that has been assigned to that Set. The Set Functions are writeonly, but the effects of a Set instruction can be read back from the individual channel's registers. The Set is given control of any channel's driver states or switches. The Set concept is a way of programming all channels on any E7804 that have been assigned to that particular SET to a particular configuration with one instruction write cycle. FunctionAddress - These addresses should all be "0". ReadBit-- Set to "0" since there is no readback for set instructions. ChanBit - Set to a "". Chan/SetAdr - These bits will denote which set is being programmed. Valid set values are 0x0 through 0x7 corresponding to the eight valid SETs. SetSelectBit - This bit is a "" because this is the SET Functions group. SET Programming Referring to Table 2, a channel's SETs Register may be programmed via the CH[0:3]_set_assign instructions. This is an independent 8-bit register per channel which determines the SETs to which the channel belongs. A channel may belong to none, one, or any combination of up to 8 sets. Programming the Driver's Source Impedance Figure shows that each driver's source impedance is programmable over a 48W to 0W range so as to match the impedance of the transmission line connecting VOP to the Device Under Test (DUT). The driver's source impedance is automatically programmed to match REREF/00, where REREF is the external reference resistor connected to the EREF pin. Initiating the source match auto-calibration sequence is a "chip function" (Table 2). Auto-calibration is performed on all channels in parallel. The Driver's source impedance is affected by its DVH and DVL levels and, therefore, auto-calibration should be initiated whenever driver levels are changed. Following auto-calibration, a driver's source impedances match (REREF/00) W when its output is at (DVH + DVL) / 2. If the output voltages of the driver are reprogrammed, then it is advised to recalibrate to maintain the best accuracy. Calibration will occur after writing the global function instruction calibrate_output_z. Calibration requires an additional 576 clock edges from CLKIN to complete the process. This is 24 instructions worth of clocks. Instructions for the device undergoing calibration may be any valid instruction except that which connects the CTC output to POUT, or simply applying the clocks without LOAD'ing instructions is also valid. At the end of the process, the new, calibrated output impedances will be applied to the driver output stage. The driver may be in the enabled or disabled state. If enabled, there could be a noticable perturbation on the output. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 4 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Bit # Hex Multiplier Binary Position Register Name Write Only = Read Only = Read/Write = no_op CHIP FUNCTIONS chip_id chip_revision calibrate_output_Z chip_switches global_calib_factor diagnostic (reserved) reserved reset CH0_relays_&_states CH1_relays_&_states CH2_relays_&_states CH3_relays_&_states reserved CH0_DVH_calib_Z CH1_DVH_calib_Z CH2_DVH_calib_Z CHANNEL FUNCTIONS CH3_DVH_calib_Z reserved CH0_DVL_calib_Z CH1_DVL_calib_Z CH2_DVL_calib_Z CH3_DVL_calib_Z reserved CH0_sw_calib_Z CH1_sw_calib_Z CH2_sw_calib_Z CH3_sw_calib_Z reserved CH0_set_assign CH1_set_assign CH2_set_assign CH3_set_assign Set0_relays_&_states Set1_relays_&_states SET FUNCTIONS Set2_relays_&_states Set3_relays_&_states Set4_relays_&_states Set5_relays_&_states Set6_relays_&_states Set7_relays_&_states reserved R/W R/W R/W R/W W0 W0 W0 W0 W0 W0 W0 W0 set7 set7 set7 set7 set6 set6 set6 set6 set5 set4 set3 set2 set1 set0 set5 set4 set3 set2 set1 set0 set5 set4 set3 set2 set1 set0 set5 set4 set3 set2 set1 set0 S6 S6 S6 S6 S6 S6 S6 S6 S5 S5 S5 S5 S5 S5 S5 S5 S4 S4 S4 S4 S4 S4 S4 S4 S3 S3 S3 S3 S3 S3 S3 S3 S2 S2 S2 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S1 S1 S1 R/W R/W R/W R/W impedance calibration code impedance calibration code impedance calibration code impedance calibration code R/W R/W R/W R/W impedance calibration code impedance calibration code impedance calibration code impedance calibration code R/W R/W R/W R/W impedance calibration code impedance calibration code impedance calibration code impedance calibration code WO R/W R/W R/W R/W INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI S6 S6 S6 S6 S5 S5 S5 S5 S4 S4 S4 S4 S3 S3 S3 S3 SETS ALL S2 S2 S2 S2 S1 S1 S1 S1 WO RO R/W WO RO RO R/W R/W R/W R/W 0x00 to 0xFF Z D12 (MSB) 23 8 22 21 010x0000 4 2 20 1 19 8 18 17 01x0000 4 2 16 1 15 8 14 13 0x1000 4 2 12 1 11 8 10 9 0x0100 4 2 8 1 7 8 6 4 5 0x0010 2 4 1 3 8 2 1 0x0001 4 2 0 1 Data Bits D0 D11 D10 0 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 (LSB) Chan/Set Adr Set Sel A3 0 x x CAL S7 x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 A2 0 x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 A1 0 x x x x x x x x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 x x x x x x x x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0/1 0/1 0/1 0/1 0/1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0 0 0 0 0 0 0 Chan Read Bit Bit Function Adr F3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 F2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 F1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 F0 0 W1 1 W2 0 W3 1 W4 0 W5 1 W6 0 W8 W9 1 W10 0 W11 0 W12 0 W13 0 W14 0 W15 1 W16 1 W17 1 W18 1 W19 1 W20 0 W21 0 W22 0 W23 0 W24 0 W25 1 W26 1 W27 1 W28 1 W29 1 W30 1 W31 1 W32 1 W33 1 W34 0 W35 0 W36 0 W37 0 W38 0 W39 0 W40 0 W41 0 W42 0 W43 0 0 (see Readback Table for data) (see Readback Table for data) 0111 - 1110 0100 - 1111 0100 - 1110 0100 - 1110 0100 - 1110 INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI INT SDEN SDHI 1000 - 1111 Table 2 . E7804 Instruction Table/Address Map (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 5 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Register Name chip_id chip_revision calibrate_output_Z chip_switches global_calib_factor diagnostic (reserved) CH0_switches_&_states CH1_switches_&_states CH2_switches_&_states CH3_switches_&_states CH0_DVH_calib_Z CH1_DVH_calib_Z CH2_DVH_calib_Z CHANNEL FUNCTIONS CH3_DVH_calib_Z CH0_DVL_calib_Z CH1_DVL_calib_Z CH2_DVL_calib_Z CH3_DVL_calib_Z CH0_sw_calib_Z CH1_sw_calib_Z CH2_sw_calib_Z CH3_sw_calib_Z CH0_set_assign CH1_set_assign CH2_set_assign CH3_set_assign Bit # 23 22 21 20 19 18 17 TRAILING 0's MSB RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 15 14 13 12 11 10 VALID DATA READBACK 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 9 8 7 6 LSB 1 0 0 0 0 0 QA QA QA QA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 QB QB QB QB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEN SEN SEN SEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 set7 set7 set7 set7 set6 set6 set6 set6 0 SDEN SDEN SDEN SDEN 0 SDHI SDHI SDHI SDHI 1 0 0 0 1 0 0 0 0 0 0 0 0 0 CAL S7 X X X X X 0 S2 S2 S2 S2 Z S1 S1 S1 S1 X X X X X X X X X X X X X X X X X set0 set0 set0 set0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X R1 X R2 X R3 X R4 X R5 X R6 X R7 X R8 X R9 X R10 X R11 X R12 X R13 X R14 X R15 X R16 X R17 X R18 X R19 X R20 X R21 X R22 X R23 X R24 X R25 X R26 5 43210 LEADING BITS Notes 1 2 GLOBAL FUNCTIONS 8-bit global cal factor 0 S6 S6 S6 S6 0 S5 S5 S5 S5 0 S4 S4 S4 S4 0 S3 S3 S3 S3 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 8-bit impedance calibration code 7-bit impedance calibration code 7-bit impedance calibration code 7-bit impedance calibration code 7-bit impedance calibration code set5 set5 set5 set5 set4 set4 set4 set4 set3 set3 set3 set3 set2 set2 set2 set2 set1 set1 set1 set1 Notes: 1 2 Device part number = 7804 decimal = 0x1E7C hex Rev A = 0x000, B = 0x001, ... Table 3 . Registers' Readback Bit Sequences (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 6 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Chip Functions Register Name no_op 0x00 Function Address Channel/Set Address don't care 0 Channel Select Bit 0x00 Set Select Bit Mode 0 or 0 Write Only Default Value Description 0 0000 0000 0000 This bit stream is used as a null stream. No operation will result if shifted in and a LOAD is executed. It is useful if multiple devices are connected in serial arrangement and a chip is not being addressed, but a parallel LOAD will occur for all devices on the serial bus. 0x01 Function Address Channel/Set Address don't care 0 Channel Select Bit 0x1E7C Register Name chip_id Set Select Bit Mode 0 or 1 Read Only Default Value Description 1 1110 0111 1100 This identifies the device part number, decimal equivalent is 7804. It is a read only register. 0x02 Function Address Channel/Set Address don't care 0 Channel Select Bit Register Name chip_revision Set Select Bit Mode 0 or 1 Read Only Default Value Description Register Name 0 0000 0000 0000 This identifies the device die revision number. The first revision is decimal 0, the second will be decimal 1, etc. It is a read only register. calibrate_output_z 0x03 Function Address Channel/Set Address don't care 0 Channel Select Bit 0x00 Set Select Bit Mode 0 or 1 Read/Write Default Value Description 0 0000 0000 0000 Writing to the LSB of this address will initiate a chip-wide calibration of the output impedances of the drivers. The internal state machine that performs the calibrations will require 21 microseconds for complete calibration of all channels. This is 30 instructions (x24 clocks) clocked at 33 MHz CLKIN. Because the calibration and Continuity Test Circuits (CTC) both share the EREF pin, z_calibration cannot occur if any CTC is switched into operation using S5. D0 - writing a one to this bit will initiate the calibration process. Once calibration is completed, this bit will readback as a 0. 0x04 Function Address Channel/Set Address don't care 0 Channel Select Bit 0x00 Register Name chip_switches Set Select Bit Mode 0 or 1 Read/Write Default Value Description 0 0000 0000 0000 This register is used to switch non-channel specific switches. D0 - writing a one to this bit will close the S7 switch. The S7 switch is a dual pole switch that connects the EPMUS and the EPMUF signals to the PMU_OUT pin. The primary use is when PMU_OUT is externally shorted to the temperature diode ANODE pin. Closing this switch will allow the external PMU to connect to the temperature diode string on an individual E7804 to perform die temperature measurements. Register Name global_calib_factor 0x05 Function Address Channel/Set Address don't care 0 Channel Select Bit 0x00 Set Select Bit Mode 0 or 1 Read/Write Default Value Description 0 0000 1111 1111 This register holds the eight-bit calibration factor based upon the resistor value on the EREF pin. The value in this register is used in calculating the output impedances of the driver outputs during calibration. After RESET it will be 0xFF. D0-D7 - the eight-bit value of the calibration factor. D0=LSB. 0x06 0 or 1 Register Name diagnostic Function Address Set Select Bit Read/Write Channel/Set Address don't care Mode 0 Channel Select Bit 0 0000 0000 0000 0x00 0x0F Function Address Channel/Set Address don't care 0 Channel Select Bit 0x00 This register is used for test access. Do not write to this register. Default Value Description Register Name reset Set Select Bit Mode 0 or 1 Write Only Default Value 0 0000 0000 0000 Description This register is used for programmable (soft) reset of the device. D0 - ALL - writing a one to this bit will perform a soft reset of the entire chip. It is wire OR'd with the external RESET* pin. The ALL reset function requires 7 clock cycles after this bit is latched in by the LOAD signal. The RESET ALL instruction will clear the SDIN and SDOUT shift registers. It is advised to follow a RESET ALL instruction with a NO_OP instruction. D1 - SETS - writing a one to this bit will perform a soft reset of all the set assignments for all the channels of the device. This SET function function requires 5 clock cycles after this bit is latched in by the LOAD signal. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 7 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions Channel Relay and States Registers Register Name CH0_switches_&_states Function Address 0x00 Channel/Set Address 0x00 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used for controlling the Channel_0 (CH0) switches. Bits are also present to control the CH0 driver state and read back the states of the CH0 comparator outputs. The comparator output states are indicated above as unknown unless the input voltage relationships are known. D0 - S1 - writing a one to this bit will close the switch that connects the driver output to the channels VIO pin. D1 - S2 - writing a one to this bit will close the switch that connects the window comparator input to the channel's VIO pin. D2 - S3 - writing a one to this bit will close the switch that connects the driver output to the external PMU sense line (EPMUS) for purposes of system diagnostics. D3 - S4 - writing a one to this bit will close the switches that connect both the external PMU bus sense (EPMUS) and force (EPMUF) lines to the channel's POUT pin. D4 - S5 - writing a one to this bit will close the switch that connects the continuity test circuit (CTC) to the channel's POUT pin. If any channel has S5 closed, then output impedance calibration cannot occur. D5 - S6 - writing a one to this bit will close the switch that connects the pull-up resistor and voltage to the channel's POUT pin. D6 - SDHI (Serial Data Hi) - writing a logical one to this bit will force the channel's driver to output the DVH voltage. Writing a zero to this bit will force the driver to output the DVL voltage. The SDHI bit will only have effect if the SEN bit (D8) in this register is set to a logical one, allowing the SDHI bit to override the state of the external DHI signal to this channel's driver. D7 - SDEN (Serial Data Enable) - writing a logical one to this bit will enable the channel's driver to output either DVH or DVL (based on the SDHI bit). Writing a zero to this bit disables the driver output to high impedance. The SDEN bit will only have effect if the SEN bit (D8) in this register is set to a logical 1, allowing the SDEN bit to override the state of the external DEN signal to this channel's driver. D8 - SEN (Serial Enable) - writing this bit to a logical one will allow the D6 and D7 bits in this register override the external driver control signals DHI and DEN. D9 - QB - this bit is a Read Only bit that is the state of the channel's comparator B output. Writing to this bit will have no effect. D10 - QA - this bit is a Read Only bit that is the state of the channel's comparator A output. Writing to this bit will have no effect. Register Name CH1_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used for controlling the Channel_1 (CH1) switches. Bits are also present to control the CH1 driver state and read back the states of the CH1 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. Function Address 0x00 Channel/Set Address 0x02 Channel Select Bit 1 Set Select Bit Mode 0 Read/Write Register Name CH2_switches_&_states Default Value Description Register Name 0 0000 0000 0000 This register is used for controlling the Channel 2 (CH2) switches. Bits are also present to control the CH2 driver state and read back the states of the CH2 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. CH3_switches_&_states Function Address 0x00 Channel/Set Address 0x03 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used for controlling the Channel 3 (CH3) switches. Bits are also present to control the CH3 driver state and read back the states of the CH3 comparator outputs. See the bit definitions above for the CH0_relay_&_switches register. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 8 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions (continued) Channel Calibration Registers _ DVH Register Name CH0_DVH_calib_z Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used to store the calibration 8-bit code for CH0's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH1_DVH_calib_z Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x01 Mode Read/Write Channel Select Bit 1 Default Value Description 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH1's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Function Address 0x01 Channel/Set Address 0x02 Channel Select Bit 1 Set Select Bit Mode 0 Read/Write Register Name CH2_DVH_calib_z Default Value Description Register Name 0 0000 0000 0000 This register is used to store the calibration 8-bit code for CH2's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. CH3_DVH_calib_z Function Address 0x01 Channel/Set Address 0x03 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used to store the calibration 8-bit code for CH3's driver impedance to DVH. Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Channel Calibration Registers _ DVL Register Name CH0_DVL_calib_z Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used to store the calibration 8-bit code for CH0's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x01 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH1's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH1_DVL_calib_z Default Value Description Register Name CH2_DVL_calib_z Default Value Description Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x02 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH2's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Function Address 0x01 Set Select Bit 0 Channel/Set Address 0x03 Mode Read/Write Channel Select Bit 1 0 0000 0000 0000 0x00 This register is used to store the calibration 8-bit code for CH3's driver impedance to DVL Data is written internally after a chipwide calibration of the output impedances has occurred. User can read back this data or write different data into the register. Register Name CH3_DVL_calib_z Default Value Description (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 9 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Channel Functions (continued) Channel Set Assignment Registers Register Name CH0_set_assign Function Address 0x01 Channel/Set Address 0x00 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used to assign CH0 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. Bit # D7 set7 D6 set6 D5 set5 D4 set4 D3 set3 D2 set2 D1 set1 D0 set0 Register Name CH1_set_assign Function Address 0x01 Channel/Set Address 0x01 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Default Value Description 0 0000 0000 0000 This register is used to assign CH1 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. Function Address 0x01 Channel/Set Address 0x02 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Register Name CH2_set_assign Default Value Description 0 0000 0000 0000 This register is used to assign CH2 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. Function Address 0x01 Channel/Set Address 0x03 Channel Select Bit 1 0x00 Set Select Bit Mode 0 Read/Write Register Name CH3_set_assign Default Value Description 0 0000 0000 0000 This register is used to assign CH3 to any or no "SETs". A logical 1 in the bit position will assign CH0 to respond to global commands for the corresponding set. See bit positions in CH0_set assign register description above. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 20 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) Set Functions Register Name Set0_switches_&_states Function Address 0x00 Channel/Set Address 0x00 Channel Select Bit 1 0x00 Set Select Bit Mode 1 Write Only Default Value Description 0 0000 0000 0000 This register is used for controlling the Set_0 (CH0) switches on any channel that has been assigned to Set_0. Bits are also present to control the channels' driver states. D0 - S1 - writing a one to this bit will close the switch that connects the driver output to the channel's VIO pin. D1 - S2 - writing a one to this bit will close the switch that connects the window comparator input to the channel's VIO pin.- S3 - writing a one to this bit will close the switch that connects the driver output to the external PMU sense line D2 (EPMUS) for purposes of system diagnostics. D3 - S4 - writing a one to this bit will close the switches that connect both the external PMU bus sense (EPMUS) and force (EPMUF) lines to the channel's POUT pin. D4 - S5 - writing a one to this bit will close the switch that connects the continuity test circuit (CTC) to the channel's POUT pin. D5 - S6 - writing a one to this bit will close the switch that connects the pull-up resistor and voltage to the channel's POUT pin. D6 - SDHI (Serial Data Hi) - writing a logical one to this bit will force the channel's driver to output the DVH voltage. Writing a zero to this bit will force the driver to output the DVL voltage. The SDHI bit will only have effect if the SEN bit (D8) in this register is set to a logical one, allowing the SDHI bit to override the state of the external DHI signal to this channel's driver. D7 - SDEN (Serial Data Enable) - writing a logical one to this bit will enable the channel's driver to output either DVH or DVL (based on the SDHI bit). Writing a zero to this bit disables the driver output to high impedance. The SDEN bit will only have effect if the SEN bit (D8) in this register is set to a logical 1, allowing the SDEN bit to override the state of the external DEN signal to this channel's driver. D8 - SEN (Serial Enable) - writing this bit to a logical one will allow the D6 and D7 bits in this register override the external driver control signals DHI and DEN. Register Name Set1_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 0x00 Set Select Bit Mode 1 Write Only Default Value Description 0 0000 0000 0000 This register is used for controlling the Set_0 (CH0) switches on any channel that has been assigned to Set_1. Bits are also present to control the channels' driver states. See the bit definitions to the Set0_relays_&_states for bit definitions. Sets 2 through 6 Register Name Set7_switches_&_states Function Address 0x00 Channel/Set Address 0x01 Channel Select Bit 1 0x00 Set Select Bit Mode 1 Write Only Default Value Description 0 0000 0000 0000 This register is used for controlling the Set_7 (CH0) switches on any channel that has been assigned to Set_7. Bits are also present to control the channels' driver states. See the bit definitions to the Set0_relays_&_states for bit definitions. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 2 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information PUV REREF CTCLV, CTCFIV DVL/H, CVA/B VXX VCC VEE VAA ANODE PMU_OUT 2 4 DGND 119 118, 120 EPMUF/S 2 4 DVL/H, CVA/B 105-108 123-126 113 112 111 109-110 117 116 115 121 114 ** 4 DHI, DEN POUT VAA 4 VCC ** 4 DHI, DEN POUT VAA 4 1,2,127,128 5 6 100-104 98 97 93-96 92 QA/B 7-10 11 VCC QA/B OPN VEE 12 13 CH[0] CH[3] 91 90 VEE OPN *** TO DUT VIO DBL DBH VDD *** * * VDD DBL DBH VIO * * 14 15 16 17, 22 19, 20 89 88 87 81, 86 83, 84 80 79 78 77 TO DUT TO DUT VIO DBH DBL VEE * * 23 24 25 26 27 28 * * VEE DBH DBL VIO TO DUT *** OPN 4 QA/B VAA VCC *** VCC 4 OPN CH[1] CH[2] 76 75 71-74 70 29-32 33 24 37-40 49-51, 53, 54 41-44 46-48 55-57 VAA QA/B 4 DHI, DEN 4 DVL/H, CVA/B POUT 69 63-66 59-62 POUT 4 DHI, DEN VDD 4 DGND 5 SDOUT, SDIN, CLKIN, LOAD, RESET DVL/H, CVA/B ** ** Figure 6. E7804 Hookup VEEs of all Channels must be connected together; same for VCCs, VAAs, VDD and GNDs. NOTE: All capacitors are 0.mF unless otherwise noted. *DBH/L capacitors are 0.47mF. **DVH/L each have 0.22mF capacitors. Not necessary for CVA/B. ***Two ferrites in series. Each 600W; 206 and 0603 package sizes. Steward Part #MI0603J60R-00 and #MI206K60R-00. See text for further explanation. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 22 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) Low Cost Pin Electronics with the E7804 Figure 7 shows 6 channels of `Low Cost' Pin Electronics featuring the E7804, E6435 (Level DACs) and E4287 (PMU). 1/4 X E6435 1/2 E4287 PMU IVMON HLV VINP Level DACs LLV IVMAX F IVMIN S - 6 channels with levels per-pin and shared PMU per 6 pins - 33 MHz clocks - PMU, -3.25V, +9.75V with 4 current ranges to 40mA - Continuity test per pin - Per-pin pull-up resistor - Compatible Power (common) supply (VCC, VDD, VEE, etc.) requirements for each chip 1 X E6435 VIO[0] POUT[0] CTC 2K Level DACs VIO[15] POUT[15] CTC 2K 4 x E7804 16 Channel Driver, Comparator Figure 7. "Low Cost", 16 Channel Pin Electronics (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 23 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) Computing Maximum Power Consumption The diagram below shows the power consumption of the E7804 as a function of clocking frequency of all channels. E7804 Total Power versus (3V) Data Rate 2.5 2.0 Power (W) 1.5 1.0 0.5 0.0 0 50 100 150 Data Rate (MHz) Typ Max system in the application (assuming an air cooled system). A heatsinking solution should be chosen to be at or below a certain thermal impedance known as Rq in units of C/ Watt. The heatsinking system is a combination of factors including the actual heatsink chosen and the selection of the intertface material between the E7804 and the heatsink itself. This could be thermal grease or thermal epoxy, and they also have their own thermal impedances. The heatsinking solution will also depend on the volume of air passing over the heatsink and at what angle the air is impacting the heatsink. There are many options available in selecting a heatsinking system. The formula below shows how to calculate the required maximum thermal impedance for the entire heatsink system. Once this is known, the designer can evaluate the options that best fit the system design and meet the required Rq. Rq(heatsink_system) = (TJmax - Tambient - P * qJC) / P where, Rq(heatsink_system) is the thermal resistance of the entire heatsink system TJmax is the maximum die temperature (00C) Tambient is the maximum ambient air temp expected at the heatsink (C) P is the maximum expected power dissipation of the E7804 (Watts) qJC is the thermal impedance of the E7804 junction to case (4C/W) The graph below uses the power estimates from the previous graph and indicates the required maximum thermal impedances required for the heatsinking system using the above formula with Tambient at 35C. Required Heatsinking Thermal Resistances All Drivers and Comparators Switching, Max Tj, Max Supplies, Process Corners, 3V into 20cm, 50ohm Transmission Line The power consumption goes up with frequency and output voltage swing. Cooling Considerations Depending on the maximum operating frequencies and voltage swings the E7804 will need to drive, it may require the use of heatsinking to keep the maximum die junction termperature within a safe range and below the specified maximum of 001/2C. The E7804 package has an internal heatspreader located at the top side of the package to efficiently conduct heat away from the die to the package top. The thermal resistance of the package to the top is the qJC (junction-to-case) and is specified at 41/2C/Watt. In order to calculate what type of heatsinking should be applied to the E7804, the designer needs to determine the worst case power dissipation of the device in the application. The graph above gives a good visual relationship of the power dissipation to the maximum operating frequency (all channels simultaneously) and driver output voltage swings. Another variable that needs to be determined is the maximum ambient air temperature that will be surrounding or blowing on the device and/or the heatsink (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 24 65 60 55 50 45 40 35 30 25 20 0 50 100 150 Data Rate (MHz) Power (W) Typ Max The value of the thermal resistance of the E7804 package www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Application Information (continued) junction to air with 400 linear feet per minute (LFPM) of airflow is specified at 22C/W. At operating points greater than or equal to this value, no additional heatsinking is needed to keep the die temperatures below the maximum 00C as long as the ambient temperature of the 400 LFPM air does not exceed 35C. More information on heatsink system selections can be read on heatsink vendors' web sites and in the Semtech Application Note #ATE-A2 Cooling High Power, High Density Pin Electronics. Protection Considerations The E7804 has ESD protection on its input and outputs. The E7804 has internal, high voltage, disconnect switches for VIO and POUT pins. When open, these provide protection against voltages input into VIO and POUT which might have damaged drivers, comparators, and other internal circuits. Power Supply Sequencing/Latch-Up Protection In order to avoid the possibility of latch-up when powering this part up (or down), be careful that the conditions listed in the Absolute Maximum Ratings are never violated. That is, the power supplies should never be reverse-polarity with respect to ground, and the input signals should never go beyond the power supply rails. Furthermore, the lower-voltage analog supplies should never be greater than the higher-voltage supplies (VAA < VCC < VXX). This can easily be implemented by utilizing the diode circuit depicted in Figure 4 for each PCB that has E7804 devices on it. The following conditions must be met at all times during power-up and power-down. . 2. 3. 4. VEE GND VAA VCC VXX GND VDD VCC VEE Analog Inputs VCC or VXX GND Digital Inputs VDD The following sequencing can be used as a guideline when powering up: . 2. 3. 4. VEE VXX VCC VAA 5. 6. 7. VDD Digital Inputs Analog Inputs The recommended power-down sequence is the reverse order of the power-up sequence. One approach to ensure that the power supply polarities do not become reversed is to use Schottky diodes, as shown in Figure 8. One set of these diodes should be used per board. The optimum type of Schottky will depend on how much current the power supplies can source. VXX VCC VDD VAA Low forward voltage drop Schottky's such as 1N5820 VEE Figure 8. Board Level Supply Diodes (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 25 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Package Information 28-Pin MQFP 4mm x 20mm x 2mm (with Internal Heat Spreader) E N 1 D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b c D D1 E E1 e L L1 R N ND N 0 aaa bbb ccc - .093 .000 .010 .075 .079 .083 .011 .007 .009 .004 .913 BSC .783 .787 .791 .677 BSC .547 .551 .555 .020 BSC .029 .035 .041 (.063) .095 .115 .135 128 38 26 0-7 .008 .003 .003 D/2 D1 A B D e/2 E/2 aaa C A-B D 4X N/4 TIPS E1 ccc C A A2 C bbb C A-B D SEATING PLANE A1 bxN e 2.35 0.00 0.25 1.90 2.00 2.10 0.27 0.19 0.23 0.11 23.20 BSC 19.90 20.00 20.10 17.20 BSC 13.90 14.00 14.10 0.50 BSC 0.73 0.88 1.03 (1.60) 2.42 2.92 3.42 128 38 26 0-7 0.20 0.08 0.08 SEE DETAIL A H c GAGE PLANE 0.25 L (L1) DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS 0 -A- , -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H- . 3. DIMENSIONS "E1" AND "D1" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 26 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Absolute Maximum Ratings Parameter Positive Analog Supply - VCC or VXX Positive Analog Supply - VAA Negative Analog Supply - VEE Digital Power Supplies - VDD Total Power Supply Ranges Digital Input Voltages Driver/Comparator Pin Comparator Only Connected Driver Connected Parametric Pin CTC and PUV not Connected CTC Connected PUV Connected Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25"" from the pin) Symbol VCC, VXX VAA VEE VDD VCC to VEE VCC to VAA Min -0.5 -0.5 -5.5 -0.5 -0.5 -0.5 Max VEE + 16 6.0 0.5 6.0 16.0 16.0 VDD + 0.5 VCC CVH + 6 DVH + 0.7 VXX VAA VAA 150 125 260 Units V V V V V V V V V V V V V C C C SDIN, CLKIN, LOAD, RESET*, OPN DGND - 0.5 VIO VIO VIO POUT POUT POUT TS TJ TSOL VEE CVL - 6 DVL - 0.7 VEE VEE 0 -65 Stresses above those listed in "Absolute Maximum Ratings" section may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Positive Analog Supply to Switches Positive Analog Power Supply - Channels Positive Analog Power Supply - Channels Negative Power Supply - Channels Total Analog Supply Range Digital, Logic Power Supplies Thermal Resistance - Junction to Case (Top) Thermal Resistance - Junction to Ambient Still Air 100 lfpm 400 lfpm Junction Temperature Symbol VXX to AGND VCC to AGND VAA to AGND VEE to AGND VCC to VEE VDD to DGND JC JA JA JA TJ 25 Min VCC 8 4.75 -5.25 12.75 3.13 3.3 4 28 25.2 22.1 100 Typ 9.5 8.25 5 -5 Max VEE + 15.0 8.5 5.5 -4.75 13.75 3.46 Units V V V V V V C/W C/W C/W C/W C Note: AGND and DGND must be connected together externally. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 27 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics Digital Inputs/Outputs Parameter Digital Inputs (CLKIN, SDIN, LOAD, RESET*, OPN) Input Low Voltage Input High Voltage Input Current Digital Output (SDOUT) Output Low Voltage Output High Voltage Output Current Low Output Current High Capacitive Load Driver Circuit Parameter Analog Inputs (DVH, DVL) High Level Low Level Input Current Driver Output (VIO) Range Driver Swing DC Output Current Output Impedance (Note 1) Output Impedance Accuracy (Note 2) HiZ Leakage (DEN= 0) (Note 3) Open Circuit Leakage (Driver, comparator disconnected) at VIO (VEE to VXX) DC Accuracy (Note 4) Offset Voltage (DVH - VIO, DVL - VIO) Gain Linearity Digital Inputs to Driver Input Voltage Range Differential Input Swing Input Current External Reference Resistor Symbol DVH DVL IIN DRNG DSWG IOUT ROUT RACC IOZ IOC Min DVL + 0.5 -0.25 -10 -0.2 0.5 -50 48 4 -1 -10 1 10 Typ Max VAA + 0.1 DVH - 0.5 20 VAA 5.4 50 110 Units V V A V V mA % A nA VIL VIH IIN Symbol Min Typ Max 0.8 Units V V nA V V mA mA pF 2.0 -200 200 0.4 VDD 2.0 15 VOL VOH IOL IOH CLOAD 2.4 -2.0 VOS -20 0.99 -0.1 0 0.24 -0.2 4.5 20 1.01 0.1 VDD VDD 0.2 11 mV V/V % FSR V V A K DHI(*), DEN(*) |Input - Input*| IIN REREF DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions", including the full range of the power supplies. Note1: At VIO = (DVH + DVL) / 2. Note2: Following calibration. Accuracy is measured as a percentage of REREF/00. Note3: Comparator disconnected. Driver leakage specified for 0 [VVIO and DVH and DVL] VAA. Note4: Offset measured with input voltage (DVL or DVH) at the minimum value, and the gain error measured with the input voltage at the maximum allowed value. Measurements made with VIO unloaded. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 28 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Comparator Circuit Parameter Analog Inputs (CVA, CVB) Voltage Range Symbol VCVA, VCVB IIN VDIFF VHYS I_BIAS IOC VOS VOD VCM VOD Min -2.0 -5 -6.0 Typ Max 5.5 30 Units V A V mV Input Current Input Differential Voltage Range [(VIO - CVA), (VIO - CVB)] Hysteresis Input Leakage (Driver disconnected) at VIO (-2.0 to +5.5V) Input Leakage (Driver, Comparator disconnected) at VIO (VEE to VXX) Offset Voltage Digital Outputs (Figure 9) Differential Output Swing Common Mode Output Voltage Range Change in VOD between Complimentary Output States 6.0 10 -5 -10 -20 250 1.125 25 10 20 450 1.375 A nA mV mV V mV 45 Continuity Test Circuit (CTC) Parameter Symbol Min Typ Max Units CTCLV (Limit Voltage) Voltage Range Input Current Offset Error Gain Error CTCFIV Input Current CTC Output Compliance Voltage IIN -2.0 -1 -20 -5 -200 CTCLV + 0.25 0.0 10 20 5 200 VAA - 1 V A mV % nA V IIN CTC Output Current (Note 1) Programmable Range Offset Gain Error ICTC -250 -15 -15 -15 15 15 A A % DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions", including the full range of the power supplies. Note1: Programmed by CTCFIV using the formula: ICTC = .09 * [CTCFIV(V) / REREF(W)]. Offset and gain are calculated from calibraiton points at 0% and 90% of the 250A full-scale range. Q* Q VOD VCM Figure 9. Comparator Outputs (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 29 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) External PMU Switches, VIO/POUT Capacitance Parameter On-Resistance (EPMU Force Switch S4 to POUT) (40mA) On-Resistance (EPMU Sense Switch S4 to POUT) (4mA) On-Resistance (EPMUF and EPMUS Switch S7 to PMU_OUT) (100A) On-Resistance (Driver Output to EPMUS Switch S3) (100A) Leakage Current @ EPMUS (all channel's switches onto EPMU bus are open) Leakage Current @ EPMUF (all channel's switches onto EPMU bus are open) Capacitance @ EPMUS (all channels' switches onto EPMUS bus are open) Capacitance @ EPMUF (all channel's switches onto EPMU bus, open) (0 to 50 MHz) Capacitance at POUT (Switches Open) (Note 1) Capacitance @ VIO (S1 = Open, S2 = Closed) Capacitance @ VIO (S1 = S2 = Closed) Leakage Current at POUT (Switches Open) (Note 1) Max Current for EPMU Force Paths Max Current for EPMU Sense Paths POUT Output Range with EPMUF +40 mA POUT Output Range with EPMUF -40 mA POUT Output Range with EPMUF 40 A PMU_OUT Leakage -10 -40 -4 VEE VEE + 2.5 VEE -1 100 100 -10 -15 15 35 12 15 38 10 40 4 VXX - 2.5 VXX VXX 1 Symbol Min Typ 40 Max 110 500 7000 7000 10 Units nA nA pF 15 pF pF pF pF nA mA mA V V V A DC conditions (unless otherwise specified): Over the full Recommended Operating Conditions" Note1: Includes the EPMU, Continuity Test and Pull-up Switches. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 30 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Pull-Up Resistor Parameter Pull-Up Resistor (including its switch) PUV Voltage Range PUV Gain Error PUV Input Current POUT Voltage Range with S6 Closed V(POUTS6) Symbol Min 1 0 -2 -3 0 Typ Max 3 VAA 2 3 VAA Units K V % A V Power Supplies Parameter Max Quiescent Power Supply Consumption (Note 1) Positive Analog Supply 1 Positive Analog Supply 2 Digital Supply Negative Power Supply Switch Power Supply Symbol ICC IAA IDD IEE IXX Min Typ 60 18 55 -45 1 Max 90 30 80 4 Units mA mA mA mA mA -80 Note1: CLKIN Low, no VIO output currents, comparators with 00W floating terminations. E7804 Typical Supply Currents versus Data Rate (500mm Transmission Line) 120 Current (mA) 100 80 60 40 20 0 0 50 100 150 Data Rate (MHz) ICC IEE IAA The above graph depicts supply current variation with respect to all the Drivers concurrently driving the same 3V output swings over frequency into a 50 unterminated transmission line while also connected to the window comparators. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 3 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics a. Analog Output 50W Transmission Line (20 inches, ~2ns) VIO 600W 0603 POUT 600W 1206 Ferrites 953W Oscilloscope 50W b. Comparator Outputs c. Comparator Input VGEN VIO 50W Q 100 Q* NOTE: Driver propagation delays specified with transmission line delay removed. Figure 10. AC Test Circuits (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 32 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Comparator Circuit (Driver S1 Open) Parameter Propagation Delay (0 to 3V Input) (Figure 16) Note 4 Note 5 Digital Output Rise and Fall Times (20% - 80%) (into 100 floating termination) Minimum Pulse Width (Note 1) Propagation Delay Matching (Note 5) Symbol Tpd(+),(-) Tpd(+),(-) Tr, Tf Min 3.5 3.0 550 6 Tpd(+),(-) 1.0 Typ Max 7.5 Units ns ns ps ns ns 6.0 Driver Circuit Parameter Propagation Delay (0 to 3V Output) (Note 2, Figure 17) Data (DHI) to Output Note 4 Note 5 Enable to HiZ (Figure 12) Enable to Output Active (Figure 12) Propagation Delay Match (Tpd(+) to Tpd(-)) (Note 5) Rise/Fall Times 0 to 800 mV (20% - 80%) 0 to 3V (10% - 90%) 0 to 5V (10% - 90%) Fmax (Note 3, Figure 13) 800 mV 3V 5V Minimum Pulse Width (Note 3, Figure 14) 0 to 800 mV 0 to 3V 0 to 5V Symbol Min Typ Max Units TPLH, TPHL TPLH, TPHL TPAZ TPZA Tpd(+) to (-) Tr/Tf Tr/Tf Tr/Tf Fmax Fmax Fmax Tpw+, Tpw- Tpw+, Tpw- Tpw+, Tpw- 3.5 3.4 3.0 3.0 6.5 5.7 6.5 6.5 1.0 2.0 2.5 3.0 ns ns ns ns ns ns ns ns MHz MHz MHz 2.4 133 133 100 3.0 3.0 4.5 ns ns ns AC Test Conditions (unless otherwise specified): "Recommended Operating Conditions." Note1: Note2: Note3: Note4: Note5: For 3V input while maintaining less than 300ps of propagation delay variation. Driver propagation delays are measured with LVDS differential logic inputs at DHI and DEN. Output delay is specified with transmission line delay removed. At less than 0% output amplitude attenuation, DVL = 0V. Over all recommended operating conditions and junction temperatures. VDD at 3.3V, VCC = 8.2V, VEE = -5V, junction temperature at 45C. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 33 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Driver Performance Parameter Driver Temp. Coefficient (pd/T) (Note 4) Driver Tpd Dispersion vs. Amplitude (Note 1, Figure 11) Driver Tpd Dispersion vs. Common Mode (Note 2, Figure 11) Driver Tpd Dispersion vs. Pulse Width (Note 3, Figure 15) Symbol Tpd/C Tpd (Swing) Tpd (cm) Tpw 0.7 0.8 0.3 Min Typ Max 10 1 1 0.4 Units ps/C ns ns ns Comparator Performance Parameter Comparator Temp. Coefficient (pd/T) Comparator Tpd Dispersion vs. Overdrive (Figure 17) Comparator Tpd Dispersion vs. Common Mode (Figure 18) Comparator Tpd Dispersion vs. Edge Rate (Figure 19) Comparator Waveform Tracking Dispersion (Figure 20) Comparator Tpd Dispersion vs. Pulse Width (Figure 21) Symbol Tpd/C Min Typ 6 1.5 1.1 0.8 3.0 0.4 Max 10 2 1.5 1.0 3.5 0.7 Units ps/C ns ns ns ns ns Internal Switches Parameter OPN Input to S1 and S2, Time to: Disconnect Connect PMU to POUT, S4, Connect/Disconnect (measured from valid LOAD and CLKIN edges) (Note 5) Symbol Min Typ Max 1 1 1 Units s s s Note1: Note2: Note3: Note4: Note5: Variation in propagation delay when DVL = 0, vary DVH from 0.5V to 5.0V. Driver Output = 0.8V swing. Common mode = .0V to 3.0V. Propagation delay change when going from long to short pulse widths. DVL = 0V, DVH = 3V. Switches S-S6 open on the fourth (4th) low-going CLKIN edge after a LOAD signal is applied. S1-S6 will close on the fifth (5th) low-going CLKIN edge. Switch S7 will open or close on the fourth (4th) low-going CLKIN edge after LOAD. (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 34 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) VIO TPLH 50% TPHL DHI* DHI Figure 11. Driver Propagation Delay Measurements VIO +0.5V 90% 10% 0.0V TPZA DEN* TPAZ Time DEN Transmission line terminated 50W to ground. Figure 12. Driver HiZ Enable/Disable Delay Measurement Definition OUT(H) = 0.8V, 3.0, 5.0V VIO OUT(H) 1 / Fmax 0.90 OUT(H) 0.0V Time Figure 13. Driver Fmax Measurement Definition (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 35 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) VOH = 0.8, 3.0, 5.0 VOL = 0V Period = 100ns VIO Tpw+ VOH VOL + 0.9 * (VOH VOL) Tpw Output Signal (VOH+VOL)/2 VOL + 0.1 * (VOH VOL) VOL Time Figure 14. Driver Minimum Pulse Width Measurement Definition Period = 100 ns; Tpw1 = 95 ns; Tpw2 = 5 ns (DHI DHI*) 0.0V Tpw,in1 Tpw,in2 Time VIO 3.0V OUTPUT: OUT(H) = 3.0V; OUT(L) = 0.0V 1.5V 0.0V Tpw,out2 Tpw,out1 Time Tpw = |(Tpw,in1 Tpw,out1) (Tpw,in2 Tpw,out2)| Figure 15. Driver Dispersion: Pulse Width Measurement Definition (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 36 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) 100% 50% 0% Tpd(+) VIO SR = 1.5V/ns CVA, CVB Tpd( ) QA*/QB* QA/QB Figure 16. Comparator Propagation Delay Measurements VGEN INPUT: Freq = 10 MHz; 50% Duty Cycle, SR = 1V/ns 20-80% Tr,f for 500 mV p-p = 0.3 ns; for 5V p-p = 3 ns 2.5V 2.5V CVA/B 250 mV 250 mV 2.5V 0.0V Time TPLH TPHL (QA - QA*) 0.0V Time Figure 17. Comparator Dispersion: Overdrive Measurement Definition (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 37 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) INPUT: Freq = 10 MHz; 500 mV pp; 0V < Vos < 5.0V 50% duty cycle, 20-80% Tr,f = 0.3 ns VGEN +5.0V CVA/B = 50% CVA/B = 50% 0.0V 0V CVA/B = 50% (QA QA*) 0.0V Tpd(+) Tpd( ) Time Figure 18. Comparator Dispersion: Common Mode Measurement Definition VGEN 3.0V INPUT: Freq = 10 MHz; 0-3.0V; 50% Duty Cycle; 0.5 ns 20-80% Tr,f 5.0 ns CVA/B = 1.5V 0.0V Time Tpd(+) Tpd( ) (QA QA*) 0.0V Time Figure 19. Comparator Input Slew Rate Measurement Definition (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 38 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) INPUT: Freq = 10 MHz; 0-3.0V; 50% Duty Cycle; 10 90% Tr,f = 1.6 ns (SR = 1.5V/ns) VGEN 3.0V 90% 50% 10% 0.0V Time Tpd1 Tpd4 (QA QA*) 0.0V Time Tpd5 (QA QA*) 0.0V Tpd2 Time Tpd6 (QA QA*) 0.0V Tpd3 Time Figure 20. Comparator Dispersion: Waveform Tracking Measurement Definition INPUT: Period = 100 ns; 1.0V pp; 5.0 ns < P.W. < 95 ns; 20-80% Tr,f = 1.0 ns VGEN 1.0V CVA/B = 0.50V 0.0V Tpw,in1 Tpw,in2 Time (QA QA*) 0.0V Tpw,out1 Tpw,out2 Time Figure 21. Comparator Dispersion: Pulse Width Measurement Definition (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 39 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) Logic Specifications (Figure 22) Parameter Set up Times (to CLKIN rising edge) SDIN LOAD Hold Times (to CLKIN rising edge) SDIN LOAD Output Delay Times (to CLKIN falling edge) SDOUT CLKIN Fmax Clock High Time Clock Low Time RESET to Clock Hold-Off Time (Note 1) RESET Pulse Width Symbol TSU_SDIN TSU_LD THLD_SDIN THLD_LD TSDOUT Fmax TCLKH TCLKL TRST_IN PW RESET Min 3 5.0 5.0 8.0 0.5 7.0 33.0 10 10 10 20 Typ Max Units ns ns ns ns ns MHz ns ns ns ns AC50 AC51 AC52 AC53 AC54 AC55 AC56 AC58 AC59 AC57 Note1: After an external RESET* event, valid input signals (SDIN and CLKIN) should be held off to allow internal gates to exit RESET. SDIN and CLKIN edges may be present before TRST_IN, but the clocked states cannot be guaranteed. The RESET signal is asynchronous on both assertion and de-assertion. SDIN TSU_SDIN THLD_SDIN TCLKH CLKIN TSDOUT TCLKL TRST_IN SDOUT THLD_LD LOAD TSU_LD RESET* PWRESET Figure 22. Logic Timing Diagram (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 40 www.semtech.com E7804 TEST AND MEASUREMENT PRODUCTS Ordering Information Model Number E7804BHFT Package 128-Pin, 14x20x2mm MQFP 0.5mm Lead Pitch (with Internal Heat Spreader) E7804 Evaluation Board EVM7804BHFT Pb This product is lead-free. Contact Information Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 (c) 2007 Semtech Corp. / Rev. 7, 02/26/07 4 www.semtech.com |
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